Invention Description
As semiconductor devices continue to increase in complexity, large-scale computing systems face growing risks of silent data corruptions (SDCs), which produce incorrect computational results without triggering conventional error detection mechanisms. Traditional post-manufacturing testing approaches are often costly, inefficient, and difficult to scale across large deployments. Recent advances in large language models (LLMs) enable the automated generation of targeted test workloads that exercise specific architectural and operational conditions. By generating workloads that induce stress conditions, such as voltage droops, LLM-based approaches can improve the detection of hidden SDCs under realistic operating environments while enhancing the scalability and effectiveness of processor reliability testing.
Researchers at Arizona State University have developed a methodology/framework that uses large LLMs to automatically generate test workloads for detecting hidden hardware errors, known as SDCs, in modern processors. By producing test programs that create stress conditions in critical processor components, the system improves the ability to uncover faults that traditional methods often miss. Unlike manual or random workload design, the approach is automated, adaptive, and scalable, making it suitable for use in both design validation and real-world deployment.
Potential Applications
- Pre-silicon validation for processor design and manufacturing
- Post-deployment monitoring of processors in cloud and high-performance computing
- Chip design companies aiming to enhance reliability testing
- Cloud service providers and data centers requiring robust error detection
- Development of commercial tools for automated workload generation and testing
Benefits and Advantages
- Automated generation of targeted test programs using LLMs
- Higher detection accuracy for silent data corruptions
- Scalable testing for large-scale computing systems
- Feedback-driven refinement and reinforcement learning optimize workload synthesis
- Applicable both before and after processor deployment
- Reduces the number of test cases needed for reliable detection