Invention Description
Silent data corruptions (SDCs) are particularly difficult to detect because they produce incorrect computational results without generating warnings or system errors. A primary cause of SDCs is voltage droop, a transient reduction in supply voltage that can induce timing violations along critical signal paths. Conventional testing techniques, including static timing analysis and delay-based testing, rely on fixed operating margins and often fail to capture the dynamic voltage fluctuations encountered under realistic workloads, allowing many droop-sensitive paths to escape detection. Although in-field monitoring tools provide additional coverage, manufacturing testing remains the primary opportunity to identify these vulnerabilities. Accordingly, there is a growing need for testing methodologies that leverage telemetry data to identify droop-sensitive paths, improve SDC detection, and enhance the reliability of modern processors and system-on-chip (SoC) devices.
Researchers at Arizona State University have developed a novel methodology that leverages telemetry data to improve detection of silent data corruptions caused by voltage droop in processors and SoC devices. Telemetry-Informed Delay Testing (TIDE) is an advanced testing methodology designed to enhance the reliability of semiconductor devices by identifying timing violations induced by voltage droop—an issue often missed by traditional testing methods. By integrating telemetry sensors that monitor real-time voltage fluctuations, TIDE correlates these signals with timing integrity results across three stages: traditional path delay testing, telemetry-informed path evaluation, and telemetry-aware delay testing. This approach targets droop-sensitive paths more effectively, enabling improved fault detection while remaining compatible with existing commercial semiconductor test flows with minimal disruption.
Potential Applications
- Testing and validation of processors and system-on-chip (SoC) devices.
- Semiconductor manufacturing quality assurance.
- Reliability enhancement in advanced semiconductor technologies.
- Licensing opportunities for semiconductor test equipment providers.
- Integration in commercial semiconductor test flows for enhanced fault coverage.
Benefits and Advantages
- Enhanced detection of silent data corruptions related to voltage droop.
- Integration with existing commercial test flows requiring minimal modifications.
- Improved targeting of droop-sensitive timing paths for focused testing.
- Reduction in costly test escapes and increased device reliability.
- Utilizes real-time telemetry data to inform and refine delay testing procedures.