Background
2D stacked semiconductors as channel materials are being actively considered for high volume manufacturing (HVM). However, there is a need for developing methods for vetting important physical characteristics that affect devices. These characteristics include layer counts, contaminations, interface control, stacking order and orientation, material quality, coverage, uniformity, and defectivity. Characterization techniques needed to monitor and tune these attributes in mass-produced devices are currently lacking.
Invention Description
Researchers at Arizona State University have developed a novel method and apparatus for the rapid qualification of electrical properties in 2D layered semiconductors. This invention includes a characterization probe that can be used for the extraction of resistivity values in atomically thin layers, where other methods are not effective. This technology presents a straightforward technique for early-stage qualification of electrical properties and is wafer-scale compatible in the manufacturing process for 2D materials. This invention enables the implementation of a rapid, automated, and lithography-free characterization method for the early screening of electrical parameters in 2D layered semiconductors.
Potential Applications
- Advanced electronics manufacturing
- Screening of new materials
- Process development of 2D materials
- Renewable energy systems
- Nanotechnology
- Semiconductor manufacturing
Benefits and Advantages
- Accelerated production cycle
- Enhanced quality control
- Cost-efficient