Case ID: M21-094P^

Published: 2021-08-10 10:14:27

Last Updated: 1666966681


Inventor(s)

Umit Ogras
Radu Marculescu
Ali Akoglu
Chaitali Chakrabarti
Daniel Bliss
Samet Arda
Anderson Sartor
Nirmal Kumbhare
Anish Krishnakumar
Joshua Mack
Ahmet Goksoy
Sumit Mandal

Technology categories

Computing & Information TechnologyPhysical Science

Technology keywords

IT
Networks
Software and Communication


Licensing Contacts

Shen Yan
Director of Intellectual Property - PS
[email protected]

Hierarchical and Lightweight Imitation Learning for Dynamic Power Management of Embedded SoCs

Background
Systems-on-chip (SoCs) should be designed to meet aggressive performance requirements while coping with limited battery capacity, thermal design power (TDP), and real-time (RT) constraints. A step in this direction consists of exploiting heterogeneity, e.g., using big cores when high performance is needed and switching to little cores otherwise. In addition, techniques such as dynamic voltage and frequency scaling (DVFS) and power gating (PG) can be used at runtime to manage the power consumption of SoCs. However, the design space of runtime decisions explodes combinatorially with the number of cores, frequency levels, and power states. Additionally, current platforms serve a wide range of applications with distinct characteristics and requirements. Thus, the immense design space and the growing variety of applications call for new runtime techniques to efficiently manage the power and performance of embedded heterogeneous platforms.

Invention Description
Researchers at Arizona State University, the University of Wisconsin-Madison, the University of Texas at Austin, the University of Arizona, and Carnegie Mellon University, have developed a hierarchical imitation learning framework that maximizes the energy efficiency while satisfying soft real-time constraints on embedded SoCs. This approach first trains dynamic power management (DPM) policies using imitation learning; then, it applies a regression policy at runtime to minimize deadline misses.

Potential Applications
•    Embedded systems-on-chip (SoCs) including applications in wireless communications and radar systems

Benefits and Advantages
•    Improves the energy-delay product by an average of 40%
•    Reduces deadline misses by up to 76% compared to state-of-the-art approaches
•    Trained policies impose negligible prediction time overhead and minimal memory footprint

Related publication: HiLITE: Hierarchical and Lightweight Imitation Learning for Power Management of Embedded SoCs

Research Homepage of Professor Umit Ogras

Faculty Profile of Professor Chaitali Chakrabarti

Faculty Profile of Professor Daniel Bliss