As the scaling of technology encounters more formidable obstacles, System-on-Chip (SoC) architects are exploring the capabilities of Domain-Specific SoCs (DSSoCs) to effectively balance performance and flexibility. DSSoC architectures are characterized by a heterogeneous collection of general-purpose cores and programmable accelerators tailored to a particular application domain. However, the design and implementation of hardware accelerators is time-consuming and complex. DSSoCs commonly operate in real-time environments where time-constrained applications arrive dynamically. For a fixed collection of heterogeneous accelerators, this requires dynamic and low-overhead scheduling strategies to enable effective runtime management and task partitioning across these accelerators. To add to these challenges, it is also crucial to provide effective toolchains by which application developers can port their applications to DSSoCs. Hence, a need persists for efficient Network-on-Chip (NoC) fabric that is tuned for a given DSSoC’s collection of accelerators.
Researchers at Arizona State University, the University of Wisconsin-Madison, the University of Texas at Austin, the University of Arizona, and Carnegie Mellon University, have developed a portable, Linux-based emulation framework to provide an ecosystem for hardware-software co-design of Domain-Specific SoCs (DSSoCs) and to enable their rapid evaluation during the pre-silicon design phase. The framework also features a prototype compilation toolchain that allows users to map monolithic, unlabeled C applications to Directed Acyclic Graph (DAG)-based applications as an alternative to requiring hand-crafted, custom integration for each application within a domain. In addition to performing functional verification separately for each of these aspects of a DSSoC, this unified environment facilitates relative performance estimates among different combinations of applications, scheduling algorithms, and DSSoC hardware configurations. With these estimates, developers can narrow their configuration space prior to performing in-depth, cycle-accurate simulations of a complete system, and thus expedite convergence to a final DSSoC design.
• Design and evaluation of domain-specific systems-on-chip (DSSoCs)
Benefits and Advantages
• Reduces investment risk of DSSoC development while speeding up the design process
• Suitable for emulating DSSoCs on various commercial off-the-shelf (COTS) heterogeneous SoCs
• Provides distinct plug-and-play integration points allowing developers to individually integrate and evaluate applications, schedulers, and accelerator IPs in a realistic and comprehensive setting
Related publication: User-Space Emulation Framework for Domain-Specific SoC Design