Dynamic and Efficient Hardware/Software Codesigns of Deep Learning Accelerators

Computing Architecture

Dynamic and Efficient Hardware/Software Codesigns of Deep Learning Accelerators

Single-Cycle Processing-in-SRAM Logic Circuit Design

Masked-Based Learning Method for Neural Network Multiple Task Adaption

Static and dynamic precision adaptation for hardware learning and classification

Flexible and Efficient XNOR Circuit Architecture for Neural Network Based Deep Learning

One-Cycle Reconfigurable In-Memory Logic for Non-Volatile Memory

Fast and Efficient Max/Min Searching in DRAM

Processing-In-Memory (PIM) Platform for mRNA Quantification

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