Analog-to-digital converters (ADCs) act as gatekeepers between physical world (analog) and data analytics (digital). In the IoT era of connected edge devices sensing various physical quantities for analysis in the cloud, ADCs need to have both high resolution (14-16 bits) and high energy efficiency at µW level power. High resolution data conversion for sensor interfaces is usually performed through delta-sigma (ΔΣ) ADCs, while high energy efficiency data conversion can be achieved using time-domain circuits that use mostly digital circuits in the signal processing chain and can leverage the advantages of CMOS technology scaling.
Recent ΔΣ ADC-first sensor front-end uses high dynamic range (> 96dB) ring voltage-controlled oscillators (VCO) for digitization since VCO-ADCs are highly digital and have been demonstrated to have high energy efficiency. However, the key limitations of VCO-ADCs for sensor front-end are (1) limited linearity which necessitates relatively high supply voltages (> 1V) to handle artifacts in sensor data; and (2) inability to handle time varying input common-mode, which is common in many sensor applications. Time varying input common-mode can easily saturate the VCO integrators, and alias VCO pulse width modulated tones into the signal band without additional front-end analog circuits (e.g., dc-servo loop circuits) that require large area passives and high-gain operational amplifiers which are challenging to design with high energy efficiency in scaled CMOS processes. Ring-amplifier based ΔΣ ADCs also show excellent energy efficiency and scalability with process and are a strong competitor to VCO-ADCs for IoT. However, ring-amplifiers need careful stabilization across process, voltage, and temperature (PVT), and both ring-amplifier and VCO ΔΣ ADCs can only handle small signal swing. There is a need for a PVT-robust ADC architecture for achieving high resolution and efficiency.
Researchers at Arizona State University have developed an analog-to-digital converter (ADC) architecture for high resolution (e.g., > 14bits) and energy efficiency (e.g., < 5fJ/conversion). The ADC architecture combines elements of voltage-controlled oscillator and successive approximation register ADCs that can monitor and correct for changes in process, voltage, and temperature (PVT) variations. The ADC architecture can be used for bandwidths in the range of 100k-5MHz.
- Analog-to-digital converter (ADC) design for:
- IoT sensor interfaces
- Bio-medical applications
- RF digitizers
- Cognitive radios
Benefits and Advantages:
- Calibration free, low-pass and band-pass highly digital ΔΣ ADCs that are robust against corner variations
- Scalable due to digital nature, able to operate from low supply voltages, and has small footprint