Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking

Semiconductor Devices

Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking

Clock Skewing Strategy to Minimize Dynamic Power and Eliminate Hold Violations in ASIC Circuits

Variable Input Resolution SRAM In-Memory Computing Architecture

Analog-To-Digital Converter (ADC) Architectures for High Resolution and Energy Efficiency

High Efficiency, Wide Voltage Gain Power Converter System

Nanotwinned Ni Films with High Strength and Ductility

Multijunction Solar Cell with Thin-Film Polycrystalline Low-Bandgap Bottom Cell

Materials and Optical Devices Based on Group IV Quantum Wells Grown on Si-Ge-Sn Buffered Silicon

Reverse Body Bias for Improved Integrated Circuit Total Ionizing Dose Response

Tunable MEMS Devices

Posts navigation

1
2
3
…
7
Next »
Last

1475 N. Scottsdale Road, Suite 200 Scottsdale, AZ 85257-3538
Phone: 480-884-1996
Fax: 480-884-1984

ASU California Center
1111 S. Broadway
Los Angeles, CA 90015
Phone: 424-229-9473
Fax: 424-238-0271

ASU Resources

ASU Enterprise Partners Knowledge Enterprise

Partner Institutions

University of Hawaii

Number one in the U.S. for innovation. ASU ahead of MIT and Stanford . - U.S. News and World Report, 8 years, 2016-2023

Maps and Locations Jobs Directory Contact ASU My ASU

Copyright and Trademark Accessibility Privacy Terms of Use Emergency COVID-19 Information