Invention Description
Fan-out wafer-level packaging (FOWLP) is an advanced packaging technology that connects multiple chiplets using copper (Cu) pillars and redistribution layers (RDLs). As chiplet-based designs become more complex, they require multi-layer RDLs, which are more prone to defects such as opens, shorts, coupling, and electromigration due to higher wiring density and current levels. Conventional testing methods are not practical for these large many-chiplet packages because they require an excessive number of test patterns.
Researchers at Arizona State University have developed SMART, a novel framework that addresses the challenges of testing FOWLPs used in multi-chiplet integration. By utilizing multi-layer redistribution layer (RDL) routing data, SMART partitions interconnects into regions to enable targeted, efficient test scheduling. This approach reduces test time and area overhead while maintaining over 99.8% fault coverage, tackling defects such as opens, shorts, and coupling issues driven by high-density multi-layer structures and electromigration. Further, the framework incorporates design space exploration to balance test performance metrics effectively.
By leveraging routing information to efficiently detect defects, this scalable and modular framework is designed to optimize testing of advanced FOWLPs and support heterogeneous integration crucial for AI, high-performance computing, and IoT applications.
Potential Applications
- Semiconductor packaging for AI accelerators and high-performance computing systems
- Testing and quality assurance of fan-out wafer-level packages in semiconductor manufacturing
- Automotive electronics requiring stringent fault detection and reliability
- Large-scale chiplet systems integration and manufacturing
- Integration of heterogeneous chiplets for IoT and edge devices
Benefits and Advantages
- Significantly reduces test time and area overhead compared to traditional methods
- Highly scalable and adaptable to large, complex package sizes and complexities
- Over 99.8% fault coverage ensuring high reliability with minimal test resources
- Enables parallel testing through effective graph partitioning
- Resource-efficient built-in self-test architecture for accurate fault diagnosis
- Enhanced targeting of realistic defects through routing-aware testing
- Optimized for modern heterogeneous multi-chiplet packages
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