Dynamic and Efficient Hardware/Software Codesigns of Deep Learning Accelerators
Algorithm Development
Dynamic and Efficient Hardware/Software Codesigns of Deep Learning Accelerators
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Supervised Graph Contrastive Learning for Few-Shot Node Classification
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Predict Enterprise Cyber Incidents by Social Network Analysis on Dark Web Forums
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Single-Cycle Processing-in-SRAM Logic Circuit Design
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Learning Sparse Features for Self-Supervised Learning with Contrastive Dual Gating
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Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference
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Multi-Aircraft Trajectory Prediction Using Bayesian Spatio-Temporal Graph Transformer Network
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Masked-Based Learning Method for Neural Network Multiple Task Adaption
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Safety-Guaranteed Driving Control of Automated Vehicles
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An infrastructure for memory management on LLM multi-core architectures
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