Dynamic and Efficient Hardware/Software Codesigns of Deep Learning Accelerators

Algorithm Development

Dynamic and Efficient Hardware/Software Codesigns of Deep Learning Accelerators

Supervised Graph Contrastive Learning for Few-Shot Node Classification

Predict Enterprise Cyber Incidents by Social Network Analysis on Dark Web Forums

Single-Cycle Processing-in-SRAM Logic Circuit Design

Learning Sparse Features for Self-Supervised Learning with Contrastive Dual Gating

Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference

Multi-Aircraft Trajectory Prediction Using Bayesian Spatio-Temporal Graph Transformer Network

Masked-Based Learning Method for Neural Network Multiple Task Adaption

Safety-Guaranteed Driving Control of Automated Vehicles

An infrastructure for memory management on LLM multi-core architectures

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