Background
Electronic devices that use clocks (e.g., smartphones, cars, GPS) require stability of timing reference signals. For wireless and wireline communications applications, short-term clock stability is an important factor, and long-term stability is less of a concern due to periodic synchronizations between the radio nodes. Short-term clock stability is especially critical for RF applications and is mostly influenced by the clock’s phase noise.
Phase noise is the random fluctuations in the phase of the signals, and is also known as timing jitter when timing is referred instead of the phase of the signals. Phase noise impacts signal-to-noise ratio (SNR), ranging accuracy, intermodulation distortion, error vector magnitude (EVM), and effective number of its (ENoB) for high-speed data conversion. There has been recent research in the area of improving phase noise and jitter in oscillators.
Invention Description
Researchers at Arizona State University have developed a new technique for improving the phase noise of clock generation circuits, including oscillators and voltage-controlled-oscillators (VCOs). This technique is versatile and does not depend on the topology of the oscillator or VCO, or the used reference signal. The phase noise improvement bandwidth is a design parameter that can be extremely wide. This technique does not require a delay-line discriminator needed in other phase noise cancellation architectures.
Potential Applications
- Improving clock accuracy in:
- Wireless industries
- Sensing & digital circuits
- Cellular wireless applications
- WiFi & radar
Benefits and Advantages
- Wide phase noise improvement bandwidth
- Does not require a delay-line discriminator
- Versatile – does not depend on topology of oscillator