Invention Description
Ferroelectric FETs (FeFETs) are three-terminal non-volatile devices that provide separate read and write paths, eliminating read-disturb issues and enabling fast, energy-efficient operation. Their steep subthreshold swing results in high ON current, extremely low OFF current, and low leakage power. Because FeFETs retain data without refresh, they offer higher bit density and significantly reduced static power consumption compared to conventional CMOS memory elements. These advantages have enabled a wide range of FeFET-based applications. Despite these advantages, FeFETs remain vulnerable to charge-trapping-induced degradation, which accumulates over time as the device experiences read, write, and erase transitions. The extent of this degradation depends on both how often transitions occur and which specific states are written, since different transitions require different programming voltages.
Researchers at Arizona State University have proposed WARP, a technique that improves multi-bit FeFET memory read reliability by adapting programmed-state currents and reference thresholds to workload-dependent device degradation. WARP is a workload-aware framework for maintaining accurate readout in multi-level ferroelectric field-effect transistor (FeFET) arrays as charge trapping shifts device currents over time. It models degradation using a compact set of representative workloads, adjusts intermediate-state programming levels, and selects statistically balanced read-reference thresholds. Lightweight on-chip workload counters and a lookup table support in-field updates without costly per-cell calibration.
WARP improves multi-bit FeFET memory read reliability by predicting workload-dependent degradation and adapting programming levels and read-reference thresholds.
Potential Applications
- FeFET-based non-volatile memory and embedded memory products
- Compute-in-memory systems and AI accelerators
- Edge devices requiring reliable, energy-efficient data storage and processing
- Reconfigurable computing fabrics, including FeFET-based FPGA structures
- Content-addressable and ternary content-addressable memory (CAM/TCAM) systems
- Next-generation semiconductor systems requiring long-term, multi-bit memory reliability
Benefits and Advantages
- Reduces read errors by up to 60%, according to the disclosed evaluation
- Adapts to workload-dependent degradation rather than relying on static thresholds
- Uses shared reference thresholds, avoiding impractical per-cell calibration
- Reduces modeling effort by representing a large workload space with a smaller set of representative workloads
- Enables in-field updates with low hardware, computational, and system overhead
- Supports reliable multi-bit storage in dense, energy-efficient FeFET arrays
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