Subthreshold Memory Cell for Analog In-Memory Computing

Analog in-memory computing (AIMC) is a computing architecture created to enable energy efficient computing beyond the current state of the art, especially when applied to neural network algorithms. Modern, state of the art graphics processing units (GPUs) and systolic array-based accelerators known as tensor processing units (TPUs) can process deep neural network inference with 8-bit weights and activations at an efficiency of approximately 1-8 tera operations per second per watt (TOPS/W) as of 2025. AIMC systems are predicted to be capable of well over 10 TOPS/W. However, AIMC has not yet been commercially successful. The most significant challenge of AIMC to date has been to achieve a neural network accuracy using an analog processor that is equivalent or close to that possible with a digital system. The accuracy of the system depends on several factors, often the most significant being the resistive memory element itself as well as the peripheral circuitry.

 

Prof. Matthew Marinella at Arizona State University and a collaborator at Sandia National Laboratories have developed a CMOS-compatible memory-cell design that improves resistive-memory accuracy for analog neural network computing. This design represents a significant improvement in the error profile of the dot product calculations, resulting in greater neural network inference accuracy. Further, this design increases effective conductance of the memory cell, reducing the total current on each column, which reduces the effect of parasitics and nonlinearity. These improvements in accuracy moves AIMC based on resistive memories much closer to commercial viability.

 

This novel memory-cell design improves the accuracy of resistive-memory-based AI accelerators by converting device conductance into a more favorable, state-dependent output.