Case ID: M16-092P^

Published: 2020-02-26 10:52:40

Last Updated: 1706109482


Sarma Vrudhula
Niranjan Kulkarni
Aykut Dengi

Technology categories

Applied TechnologiesComputing & Information TechnologyPhysical ScienceSemiconductor Devices

Technology keywords

Integrated Circuits
Materials and Electronics

Licensing Contacts

Shen Yan
Director of Intellectual Property - PS
[email protected]

Clock Skewing Strategy to Minimize Dynamic Power and Eliminate Hold Violations in ASIC Circuits

In digital systems, the difference in the arrival times at two registers is referred to as the clock skew between those registers. Clock skewing is a widely used optimization technique in conventional application-specific integrated circuit (ASIC) designs and typically implemented by introducing buffers to ensure clocking of components happens in the right order. Traditionally, clock skewing uses combinational buffers to delay the clock signal received by flipflops. However, these buffers must create precise delays to ensure the data is held long enough and prevent a hold violation. In conventional systems, circuits are designed with additional buffering to prevent such violations. However, this slows the chip down and also requires additional space and energy. Therefore, there is a need for an effective and fast clock skewing method.

Researchers at Arizona State University have invented a new approach for the generation and utilization of skewed clocks for the purpose of reducing dynamic power without sacrificing performance. A new clock skewing method (SygnalC) is used to reduce the dynamic power of ASIC circuits. SygnalC can eliminate hold-time violations without introducing buffers. Evaluation of SygnalC on various pipelined circuits demonstrates significant improvements in the dynamic power, area, and leakage. Additionally, a new flipflop (SygnalFF) generates a completion detection signal, which is a skewed input clock. Flipflops receiving a skewed clock have a timing slack at their inputs which can reduce the area and power of their fan-in logic cone. This new method allows for in-place optimization of digital circuits instead of a complex synthesis of the clock tree from scratch. Additionally, the use of skewed clocks to eliminate hold violations has a unique advantage over existing methods because it uses no buffers or latches in the datapath.


Issued Patent: U.S. Pat. No. 10,551,869


Related publication: A clock skewing strategy to reduce power and area of ASIC circuits


Potential Applications:

  • ASIC circuits
  • Process Controls
  • Circuit Design
  • Semiconductors
  • Electronics

Benefits and Advantages:

  • Faster – Increased speed due to the elimination of buffers.
  • Robust – Completion detection ensures no hold variation.
  • Smaller – Eliminating additional buffers allows for 33% smaller circuitry.
  • Reduced Power Consumption – This method uses 44% less energy.
  • Increased Efficiency – Reduced leaks by over 50%.